This invention relates to an EEPROM (electrically erasable and programmable ROM) cell using floating-gate MOS transistors and in particular to an EEPROM cell which does not require the ERASE mode of operation.
In a conventional memory device with EEPROM cells using floating-gate transistors, the ON and OFF conditions of each cell correspond to the charged or uncharged condition of its floating gate. Before entering any data to such a memory device, the user must carry out a so-called ERASE operation and set all memory cells in OFF (or ON) conditions and thereafter a so-called WRITE operation is performed whereby the charge conditions of the floating-gates are selectively changed. An example of such ERASE and WRITE operations will be explained below by way of FIG. 4.
FIG. 4 shows an example of conventional cell configuration with bit lines 3, 4 and 5 containing word select transistors 1 having their gates connected in common to a word line (select gate) 2 and a row of memory transistors 6 having their control gates 7 connected in common and their floating-gates shown at 8, 9 and 10. With a cell configuration of this type, an ERASE operation must be performed before each time new information is written in. In the case of the example shown in FIG. 4, this is achieved by applying a high voltage to the control gate 7. Electrons then flow into the floating-gates 8, 9 and 10 from the substrates through thin insulative layers such that all memory cells will be in charged conditions, or in OFF conditions. Thereafter, a high voltage is applied to the select gate 2 to select specified addresses, voltage at the control gate 7 is lowered, and then a high voltage is applied to a bit line 3, 4 or 5, causing electrons to be released from the corresponding floating gate 8, 9 or 10 to the substrate.
In summary, both the ERASE and WRITE modes of operation are required when the content of a conventional memory device of the type shown in FIG. 4 is changed (or rewritten). This means that it takes a relatively long time to rewrite the content of the memory device and such devices require complicated external circuits.